KiCAD files for Ksoloti 0.6?

Hi there! I appreciate seeing the schematic of the Ksoloti as I have learned a few things from it. I was wondering if you also shared the KiCAD board files anywhere? I’d love to know how many layers you used and how you fanned out the STM chip and connected the DRAM. Also, how you located the USB and power chips, and bypass caps. Thanks!

I’m just learning PCB design and am doing simple stuff with KiCAD and STM32s (LQFP-64 for now). Viz:

I think while the schematic is open source, I don’t think the actual KiCad project is, but from the looks of your project I think you are a bit past just learning, lol. It looks very cool!

From what I remember I think he said he used a 4 layer PCB.

Hi, yes it is a 4-layer board and all planes are GND except down left in the analog audio section, where three planes are GNDA and one (inner2) is 3.3VA.

The board files are currently not available because I can’t be arsed to be answering floods of “support requests” saying “I had the PCB made but it isn’t working!”, sorry about that.

But if anyone plans to design something in relation to the Axoloti/Ksoloti system I’d be happy to provide hardware files, depending on the project details.

Nothing special here to be honest, the SDRAM is under 100 MHz so I can get away with a loose design. Which doesn’t mean I did a loose design haha. Older revisions of the Core had the SDRAM lines running on the bottom layer but at one point I switched those to an inner layer (when board options with 1oz copper on inner layers became affordable).

Anyway what is most important is that these lines have an uninterrupted GND plane (or power, but I usually don’t do that) on the other side of the dielectric. Also important is that the length discrepancy of the respective signal groups (A0-A11, D0-D15 etc.) is not too high. But anything within a total length of a few inches should be fine.

The purple lines are the SDRAM on inner2. A few are going a bit on the top layer and inner1 before switching to inner2 and running up to the MCU. Some have squiggly lines for some length matching, because there was space.

Again, what is important is that wherever these SDRAM lines run, there (ideally) should be an uninterrupted GND plane on the bottom layer to “hold them tight”. Because as Rick Hartley emphasizes in his lectures, “the energy doesn’t travel inside the metal trace, it runs in the dielectric space under it.” Something like that.

inner2:

bottom layer:

Hmm not sure if there is any importance except bypass caps should be close to the ICs, and digital power as well as any high-frequency signals should be a good distance away from noise-sensitive circuits like audio. That’s why I have that little audio pen down left with ferrites for both 3.3V(A) and GND(A). Some believe ferrites make a difference, some don’t, all I can say is without ferrites filtering 5V (and even GND) coming in from USB, early Ksoloti prototypes had crackly noise issues.

You can see the area around the connectors and U4, U5, U6, U7 marked with white squares (not the light yellow of the silkscreen). It is a mess at first glance and not ideal if you’d follow textbooks and datasheets strictly, but this is how it came out with the space available.

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AltCircuits: I think you are a bit past just learning

I appreciate the sentiment, thank you. However, except for one other layout (following Phil’s Lab for an STM32 board in KiCAD), this is my first board! :slight_smile: So, I definitely have a lot to learn. I should be getting the built board late next week from JLCPCB. We’ll see if it works.

Ksoloti: Various posts

Thanks for the details! This is super interesting. Your board is so dense. That is something I need to learn too. You also seem to use super tiny components spaced very close together. I need to know how to pick smaller components and how to space them.

Things to learn:

  • How to fan out a 144-pin package - I had enough trouble with my 64-pin version
  • How close can I run traces? How small can they be?
  • How do physically smaller components differ from physically larger? (Aside from difference in hand manufacturability.)
  • (As mentioned) How to do SDRAM interface.

Things I want to do:

  • Use a 144-pin STM32H7
  • Use SDRAM and some external persistent memory (flash) for configuration
  • Have both USB Host and Device active simultaneously
    • Use either for power
  • Have a battery
  • Add a small display (SPI)
  • Add some test points in appropriate points
  • Incorporate Bluetooth/WIDI MIDI
  • Incorporate a USB Hub for multiple USB MIDI devices
  • Add an RTC & RTC battery
  • Add a dedicated USB-UART host debug I/O port

The software part I’m very confident on, having been doing that for decades. :slight_smile:

Thanks!

I have watched many of his videos, including the famous one about how signals propagate and having ground (or power) nearby; thanks for the reminder.

So, if you don’t mind a question about the SDRAM traces? I note that some of your signal vias have (what look like) nearby ground vias, but some don’t. In my board (linked above) I attempted to put these ground vias next to every single signal via, even the “DC” ones (like buttons and switch inputs) and think I succeeded. How do you know when and where it is okay to omit these, or how far one of them can be shared?

For example, this section has just one ground via with a bunch of pins:

Cropped 2024-11-02 14_28_12-ksoloti_core_v06 — PCB Editor

without ferrites filtering 5V (and even GND) coming in from USB, early Ksoloti prototypes had crackly noise issues.

Good to know. I will make sure to try those. Thanks!

Is connecting the USB case together with traces (your S1 pads and green traces) typical/good practice? I didn’t do anything with mine.

Who did you use for manufacturing and assembly? Do you recommend them?

Appreciate the engagement, understand if you’re unable to answer. Plenty to learn just by observing.

How I know when and where to omit these, is when there is no space! Each via has a track going somewhere else on another layer so you can’t place a GND via there.

I mean it is probably okay to omit these everywhere, just like it is probably okay to ride a motorcycle without a helmet. I don’t know enough about electricity to even guess where and how current is flowing and how to design a short ground return path and whatever. I placed GND vias wherever it looked feasible (and where it looked like there’d be no risk of manufacture messing it up). Now that I am looking at that area again, I see more places where I could place another transfer via (GND), I guess I made so many edits that in the end I didn’t check for those vias anymore.

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I was looking at the schematic and although I see the ferrites, it doesn’t show what values were used. Can you please share? I don’t see any markings on the devices on either of my Ksolotis. Thanks!

Those are 100 ohm @ 100 MHz for no particular reason other than availability. Any value should be fine because we’re filtering DC here and we’re not doing anything high frequency either.